Input buffers are currently used in Very Large Scale Integrate (VLSI) chips to buffer between, for example, an outside driver and inside logic. Input voltage levels for the high state (H) and the low state (L) are not the same as the high voltage power supply VDD and the low voltage power supply VSS. An input buffer converts H and L input voltage levels into internal H and L voltage levels, which are the high voltage power supply VDD and the low voltage power supply VSS.
There are generally two kinds of input buffers: static logic input buffers, such as inverter, NOR, and NAND types, and differential amplifier input buffers. In differential amplifier input buffers, the reference voltage, Vref, is typically provided by external chips. Thus, input voltage levels are defined by the reference voltage Vref, such as Vref+300 mV for H level and Vref−300 mV for L level. The voltage level of the reference voltage Vref is generally equal to half VDDQ where VDDQ is the power supply of DQ drivers in general, which is ½[VDD−VSS].
When a differential type input buffer is used, the value of the reference voltage Vref varies. A design consideration for using an input buffer includes matching the duty cycle of input and output signals. If the duty cycles are not well matched, a portion of the setup and hold time windows of the input signal are lost. Most input buffer designs are based on a target reference voltage, and therefore, there is duty cycle mismatch when the reference voltage Vref is shifted up or down from the target value.
Referring to FIG. 1, a conventional differential input buffer 100 includes a differential amplifier 150 and a buffering inverter 170. Differential input buffer 100 includes transistors 10, 20, 30, 40, 50, 60. The sources of transistors 10 and 30 are connected to VDD. The drain of transistor 10 is connected to the drain of transistor 20 at node b and equal the voltage at node b Vb. The gates of transistors 10 and 30 are also connected to the drain of transistor 20 at Vb. The sources of transistors 20 and 40 are connected at node a and equal the voltage at node a Va. Current source 1152 is located between node a and ground. The drains of transistors 30 and 40 are connected at node c and equal the voltage at node c Vc. The gate of transistor 20 is connected to the reference voltage Vref. The gate of transistor 40 is connected to an input voltage Vin. The gates of transistors 50 and 60 are connected to the drains of transistors 30 and 40 and equal the voltage at node c Vc. The drains of transistors 50 and 60 are connected and equal the output voltage Vout. The source of transistor 50 is connected to VDD. The source of transistor 60 is connected to ground.
The differential amplifier 150 is controlled by a constant current source I 152 and has two inputs: the reference voltage Vref 154 and an input voltage Vin 156. For example, when the input voltage Vin 156 equals Vref+300 mV, the input voltage Vin 156 is compared to the reference voltage Vref 154, and the output of the differential amplifier Vc and the output of the buffering inverter Vout equal the low state L and the high voltage power supply VDD, respectively. When the input voltage Vin 156 equals Vref−300 mV, the output of the differential amplifier Vc and the output of the buffering inverter Vout equal the high range H and the low voltage power supply VSS, respectively.
There is a duty cycle mismatch in a conventional input buffer when the reference voltage Vref 154 varies. For example, consider the case where VDD=2V, Vref=1V, Va=0.4V, and the logic threshold voltage equals 1V. If the input voltage Vin 156 equals the reference voltage Vref 154, then the output of the differential amplifier Vc should equal the value of the logic threshold voltage of the buffering inverter 170 (i.e., 1V), and the output of the buffering inverter Vout should also equal the reference voltage Vref 154. If the input voltage Vin 156 is greater than the reference voltage Vref 154, then the output of the differential amplifier Vc is less than the reference voltage Vref 154 so that the output of the buffering inverter Vout equals the high voltage power supply VDD. Since the logic threshold voltage of buffering inverter equals 1V in this case, the transistor ratio P3/N3 is set to provide a 1V inverter threshold voltage.
If the reference voltage Vref 154 equals 1.2V (Vref increased by 200 mV), the voltage Va would also be increased by 200 mV to provide the same current I at current source 152. Accordingly, the output of the differential amplifier Vc is also increased. Since the inverter threshold voltage is still 1V, the buffering inverter 170 tends to generate a low state voltage level L. Thus, the buffering inverter operation is slower for an input of a high state voltage level H and faster for an input of a low state voltage level L.
If the reference voltage Vref 154 equals 0.8V (Vref is now lowered by 200 mV), the situation is opposite. That is, voltage Va and the output of the differential amplifier Vc are 200 mV lower so that the buffering inverter operation is slower for an input of a low range voltage level L and faster for an input of a high state voltage level H.
Likewise, using an existing differential type input buffer, there is a propagation delay mismatch between the high and low range input voltage levels H and L when there is a variation in the reference voltage Vref 154. As a result, setup and hold time windows are affected and there is potential for malfunction.
A method of better matching the duty cycles of the input and output signals to keep necessary signal delays in spite of variation in the reference voltage Vref is desirable.